1. Field of the Invention
The present invention relates to a dynamic type semiconductor memory device (DRAM), and more particularly to a dynamic type semiconductor memory in which the interference noise between bit lines can be small.
2. Description of the Related Art
Recent improvement of memory cell structure and recent progress in micro-processing technology have much enhanced the integration density of DRAMs which are semiconductor memories having memory cells each comprised of one transistor and one capacitor. The higher the integration density of a DRAM, the shorter the distance between any adjacent two bit lines through which the data stored in the memory-cell array is read to be amplified by an sense amplifier. The shorter this distance, the greater the coupling capacitance between the bit lines, and the larger the interference noise therebetween inevitably. As is known in the art, the interference noise between the bit lines is a prominent cause of inaccurate reading of data from the DRAM.
To solve this problem it has been proposed that any two adjacent bit lines be twisted, thereby to reduce the interference noise, as is disclosed in Published Unexamined Japanese Patent Application No. 63-148489 and also in ISSCC 88 Digest of Technical Papers, pp. 238-239. When the bit lines are twisted, the interference noise is reduced, but not sufficiently, and the memory-cell array becomes more complex inevitably.
In summary, the conventional DRAMs are disadvantageous in two respects. First, a considerably large interference noise is generated between any adjacent bit lines due to the coupling capacitance between them. Secondly, when the bit lines are twisted, the memory-cell array inevitably becomes complicated.